1. Technical Field
The disclosure generally relates to formation of semiconductor elements, and specifically to performing a via first trench last (VFTL) process in a die seal area of a semiconductor device.
2. Related Art
In semiconductor device manufacturing, it is often necessary to use metal fill technology to form metal in a dielectric trench and via for interconnecting different layers and/or different metal materials in the semiconductor device. One such metal fill process is commonly referred to as a “damascene” process, in which dielectric layers are first etched, and then filled with a desired metal material. There are two types of commonly-used damascene processes: (1) single damascene—separately etching and filling a trench (used for inter-level connections) and a via (used for intra-level connections); and (2) dual damascene—etching the trench and via, and then filling them together at the same time. Generally, dual damascene is preferred over single damascene processes due to reduced manufacturing costs, etc. FIG. 1A illustrates an preferred semiconductor cross-section after an ideal dual damascene etch. However, various process conditions often cause resulting profiles to be deviated from the desired profile. For purposes of the following discussion, FIGS. 1B and 1C illustrate exemplary semiconductor devices that result from conventional dual damascene processes, and which include an upper dielectric 130, a lower dielectric 120, a via 150, and a trench 155.
There are two preferred types of dual damascene processes that are common in the industry: Trench first via last (TFVL) and via first trench last (VFTL). In TFVL, as its name implies, the trench is etched prior to the via. For example, a first mask is used to define a width of the trench. The device is then etched, using the first mask as a guide to etch the trench in an upper dielectric. Following the creation of the trench, a second mask is patterned within the trench to define a width of the via. A second etch is then performed, using the second mask as a guide, to form the via in a lower dielectric. Once the trench and via have been formed, they are filled with a metal material, such as copper, for example. In VFTL, on the other hand, the via is etched before the trench. In particular, a first mask is used to define the width of the via. The via is formed by etching, using the first mask as a guide, through both an upper and lower dielectric. Once the via has been formed, a spin-on planarization process are used to fill the via holes and provide better pattern process windows. Usually, spin on organic (e.g., resist or organic BARC) or dielectric materials (e.g., spin-on-glass (SOG) or spin on low k materials) are used to fill the via holes and to planarize the wafer surface. After surface planarization, a second mask is formed over the upper dielectric to define a width of the trench. The trench is then formed by etching, using the second mask as a guide, through only the upper dielectric.
As mentioned above, in these conventional VFTL processes a planarization step using a spin technique is used to fill the via holes and to planarize the wafer surface. As a result, the spin-on underlayer may not have uniform thickness among all areas of the semiconductor device. For example, the spin on layer may be thicker in isolated via holes or areas having no vias of the semiconductor device and thinner in the area where via holes are more dense. The thinnest spin on layer will be in a die seal area (e.g., an area of the semiconductor die having a continuous trench line located at the edge of the device area, which is used to stop cracks caused during a cutting process from harming the functional areas), where the trenches are larger and require more spin on materials to fill the trench holes. As a result of the non-uniform coating of the spin on layer, a subsequent etching process may cause defects in the semiconductor device that can greatly affect performance.
For example, FIG. 1A illustrates a side view of the desired semiconductor device profile resulting from a VFTL process. FIGS. 1B and 1C illustrate deviations from the desirable profile and can be easily found in many semiconductor devices that employ VFTL approaches. In each area, an etch-stop layer 115, a via tetraethylorthosilicate (TEOS) layer 120 (e.g., lower dielectric layer), a silicon layer 125, a trench TEOS layer 130 (e.g., upper dielectric layer), and a silicon-rich nitride layer 135 are formed over a substrate 110, separated by a via 150 and a trench 155.
As shown in FIG. 1B, when the spin on layer is too thick, the subsequent etching of the conventional processes produces undesired fencings 190 in the final structure. Similarly, as shown in FIG. 1C, when the spin on layer is too shallow, the etching of the conventional processes produces undesired sub-trenches 195. Both the fencings 190 and the sub-trenches 195 can cause reliability concerns and defects, which will greatly affect performance of the device. Therefore, it is desired to perform the VFTL processes in a manner that can prevent the formation of these defects in order to enhance device performance and manufacturing yield.